? 2002 fairchild semiconductor corporation ds500040 www.fairchildsemi.com august 1997 revised october 2002 74vcx162244 low voltage 16-bit buffer/line driver with 3.6v tolerant inputs and outputs and 26 ? series resistor in outputs 74vcx162244 low voltage 16-bit buffer/line driver with 3.6v tolerant inputs and outputs and 26 ? series resistor in outputs general description the vcx162244 contains sixteen non-inverting buffers with 3-state outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. the device is nibble (4-bit) controlled. each nibble has separate 3-state control inputs which can be shorted together for full 16-bit operation. the 74vcx162244 is designed for low voltage (1.2v to 3.6v) v cc applications with i/o capability up to 3.6v. the 74vcx162244 is also designed with 26 ? series resistors in the outputs. this design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. the 74vcx162244 is fabricated with an advanced cmos technology to achieve high speed operation while maintain- ing low cmos power dissipation. features 1.2v to 3.6v v cc supply operation 3.6v tolerant inputs and outputs 26 ? series resistors in outputs t pd 3.3 ns max for 3.0v to 3.6v v cc power-off high impedance inputs and outputs supports live insertion and withdrawal static drive (i oh /i ol ) 12 ma @ 3.0v v cc uses patented noise/emi reduction circuitry latch-up performance exceeds 300 ma esd performance: human body model > 2000v machine model > 200v also packaged in plastic fine-pitch ball grid array (fbga) note 1: to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ordering code: note 2: ordering code ?g? indicates trays. note 3: devices also available in tape and reel. specify by appending suffix letter ?x? to the ordering code. logic symbol order number package number package description 74vcx162244g (note 2)(note 3) bga54a 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide 74vcx162244mtd (note 3) mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide
www.fairchildsemi.com 2 74vcx162244 connection diagrams pin assignment for tssop pin assignment for fbga (top thru view) pin descriptions fbga pin assignments truth tables h = high voltage level l = low voltage level x = immaterial (high or low, inputs may not float) z = high impedance pin names description oe n output enable input (active low) i 0 ? i 15 inputs o 0 ? o 15 outputs nc no connect 123456 a o 0 nc oe 1 oe 2 nc i 0 b o 2 o 1 nc nc i 1 i 2 c o 4 o 3 v cc v cc i 3 i 4 d o 6 o 5 gnd gnd i 5 i 6 e o 8 o 7 gnd gnd i 7 i 8 f o 10 o 9 gnd gnd i 9 i 10 g o 12 o 11 v cc v cc i 11 i 12 h o 14 o 13 nc nc i 13 i 14 j o 15 nc oe 4 oe 3 nc i 15 inputs outputs oe 1 i 0 ?i 3 o 0 ?o 3 ll l lh h hx z inputs outputs oe 2 i 4 ?i 7 o 4 ?o 7 ll l lh h hx z inputs outputs oe 3 i 8 ?i 11 o 8 ?o 11 ll l lh h hx z inputs outputs oe 4 i 12 ?i 15 o 12 ?o 15 ll l lh h hx z
3 www.fairchildsemi.com 74vcx162244 functional description the 74vcx162244 contains sixteen non-inverting buffers with 3-state outputs. the device is nibble (4 bits) con- trolled with each nibble functioning identically, but indepen- dent of each other. the control pins may be shorted together to obtain full 16-bit operation.the 3-state out- puts are controlled by an output enable (oe n ) input. when oe n is low, the outputs are in the 2-state mode. when oe n is high, the standard outputs are in the high imped- ance mode but this does not interfere with entering new data into the inputs. logic diagram
www.fairchildsemi.com 4 74vcx162244 absolute maximum ratings (note 4) recommended operating conditions (note 6) note 4: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rat- ings. the ? recommended operating conditions ? table will define the condi- tions for actual device operation. note 5: i o absolute maximum rating must be observed. note 6: floating or unused inputs must be held high or low. dc electrical characteristics (2.7v < v cc 3.6v) supply voltage (v cc ) ? 0.5v to + 4.6v dc input voltage (v i ) ? 0.5v to + 4.6v output voltage (v o ) outputs 3-state ? 0.5v to + 4.6v outputs active (note 5) ? 0.5v to v cc + 0.5v dc input diode current (i ik ) v i < 0v ? 50 ma dc output diode current (i ok ) v o < 0v ? 50 ma v o > v cc + 50 ma dc output source/sink current (i oh /i ol ) 50 ma dc v cc or gnd current per supply pin (i cc or gnd) 100 ma storage temperature range (t stg ) ? 65 c to + 150 c power supply operating 1.2v to 3.6v data retention only 1.2v to 3.6v input voltage ? 0.3v to + 3.6v output voltage (v o ) output in active states 0v to v cc output in 3-state 0.0v to 3.6v output current in i oh /i ol v cc = 3.0v to 3.6v 12 ma v cc = 2.3v to 2.7v 8 ma v cc = 1.65v to 2.3v 3 ma v cc = 1.4v to 1.6v 2 ma v cc = 1.2v 100 a free air operating temperature (t a ) ? 40 c to + 85 c minimum input edge rate ( ? t/ ? v) v in = 0.8v to 2.0v, v cc = 3.0v 10 ns/v symbol parameter conditions v cc min max units (v) v ih high level input voltage 2.7 - 3.6 2.0 v 2.3 - 2.7 1.6 1.65 - 2.3 0.65 x v cc 1.4 - 1.6 0.65 x v cc 1.2 0.65 x v cc v il low level input voltage 2.7 - 3.6 0.8 v 2.3 - 2.7 0.7 1.65 - 2.3 0.35 x v cc 1.4 - 1.6 0.35 x v cc 1.2 0.5 x v cc v oh high level output voltage i oh = ? 100 a 2.7 - 3.6 v cc - 0.2 v i oh = ? 6 ma 2.7 2.2 i oh = ? 8 ma 3.0 2.4 i oh = ? 12 ma 3.0 2.2 i oh = ? 100 a 2.7 - 3.6 v cc - 0.2 i oh = ? 4 ma 2.3 2.0 i oh = ? 6 ma 2.3 1.8 i oh = ? 8 ma 2.3 1.7 i oh = ? 100 a 1.65 - 2.3 v cc - 0.2 i oh = ? 3 ma 1.65 1.25 i oh = ? 100 a 1.4 - 1.6 v cc - 0.2 i oh = ? 1 ma 1.4 1.05 i oh = ? 100 a 1.2 v cc - 0.1
5 www.fairchildsemi.com 74vcx162244 dc electrical characteristics (2.7v < vcc 3.6v) (continued) note 7: outputs disabled or 3-state only. ac electrical characteristics (note 8) note 8: for c l = 50 p f, add approximately 300 ps to the ac maximum specification. note 9: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). symbol parameter conditions v cc min max units (v) v ol low level output voltage i ol = 100 a 2.7 - 3.6 0.2 v i ol = 6 ma 2.7 0.4 i ol = 8 ma 3.0 0.55 i ol = 12 ma 3.0 0.8 i ol = 100 a 2.7 - 3.6 0.2 i ol = 6 ma 2.3 0.4 i ol = 8 ma 2.3 0.6 i ol = 100 a 1.65 - 2.3 0.2 i ol = 3 ma 1.65 0.3 i ol = 100 a 1.4 - 1.6 0.2 i ol = 1 ma 1.4 0.35 i ol = 100 a 1.2 0.1 i i input leakage current 0 v i 3.6v 1.2 - 3.6 5.0 a i oz 3-state output leakage 0 v o 3.6v 1.2 - 3.6 10 a v i = v ih or v il i off power-off leakage current 0 (v i , v o ) 3.6v 0 10 a i cc quiescent supply current v i = v cc or gnd 1.2 - 3.6 20 v cc (v i , v o ) 3.6v (note 7) 1.2 - 3.6 20 a ? i cc increase in i cc per input v ih = v cc ? 0.6v 2.7 - 3.6 750 a symbol parameter conditions v cc t a = ? 40 c to + 85 c units figure (v) min max number t phl , propagation delay c l = 30 pf, r l = 500 ? 3.3 0.3 0.8 3.3 ns figures 1, 2 t plh 2.5 0.2 1.0 3.8 1.8 0.15 1.5 7.6 c l = 15 pf, r l = 2k ? 1.5 0.1 1.0 15.2 figures 5, 6 1.2 1.5 38 t pzl , output enable time c l = 30 pf, r l = 500 ? 3.3 0.3 0.8 3.8 ns figures 1, 3, 4 t pzh 2.5 0.2 1.0 5.1 1.8 0.15 1.5 9.8 c l = 15 pf, r l = 2k ? 1.5 0.1 1.0 19.6 figures 5, 7, 8 1.2 1.5 49 t plz , output disable time c l = 30 pf, r l = 500 ? 3.3 0.3 0.8 3.6 ns figures 1, 3, 4 t phz 2.5 0.2 1.0 4.0 1.8 0.15 1.5 7.2 c l = 15 pf, r l = 2k ? 1.5 0.1 1.0 14.4 figures 5, 7, 8 1.2 1.5 36 t oshl output to output skew c l = 30 pf, r l = 500 ? 3.3 0.3 0.5 ns t oslh (note 9) 2.5 0.2 0.5 1.8 0.15 0.75 c l = 15 pf, r l = 2k ? 1.5 0.1 1.5 1.2 1.5
www.fairchildsemi.com 6 74vcx162244 dynamic switching characteristics capacitance symbol parameter conditions v cc t a = + 25 c units (v) typical v olp quiet output dynamic peak v ol c l = 30 pf, v ih = v cc , v il = 0v 1.8 0.15 v 2.5 0.25 3.3 0.35 v olv quiet output dynamic valley v ol c l = 30 pf, v ih = v cc , v il = 0v 1.8 ? 0.15 v 2.5 ? 0.25 3.3 ? 0.35 v ohv quiet output dynamic valley v oh c l = 30 pf, v ih = v cc , v il = 0v 1.8 1.55 v 2.5 2.05 3.3 2.65 symbol parameter conditions t a = + 25 c units typical c in input capacitance v cc = 1.8, 2.5v or 3.3v, v i = 0v or v cc 6pf c out output capacitance v i = 0v or v cc , v cc = 1.8v, 2.5v or 3.3v 7 pf c pd power dissipation capacitance v i = 0v or v cc , f = 10 mhz, v cc = 1.8v, 2.5v or 3.3v 20 pf
7 www.fairchildsemi.com 74vcx162244 ac loading and waveforms (v cc 3.3v 0.3v to 1.8v 0.15v) figure 1. ac test circuit figure 2. waveform for inverting and non-inverting functions figure 3. 3-state output high enable and disable times for low voltage logic figure 4. 3-state output low enable and disable times for low voltage logic test switch t plh , t phl open t pzl , t plz 6v at v cc = 3.3 0.3v; v cc x 2 at v cc = 2.5 0.2v; 1.8 0.15v t pzh , t phz gnd symbol v cc 3.3v 0.3v 2.5v 0.2v 1.8v 0.15v v mi 1.5v v cc /2 v cc /2 v mo 1.5v v cc /2 v cc /2 v x v ol + 0.3v v ol + 0.15v v ol + 0.15v v y v oh ? 0.3v v oh ? 0.15v v oh ? 0.15v
www.fairchildsemi.com 8 74vcx162244 ac loading and waveforms (v cc 1.5v 0.1v to 1.2v) figure 5. ac test circuit figure 6. waveform for inverting and non-inverting functions figure 7. 3-state output high enable and disable times for low voltage logic figure 8. 3-state output low enable and disable times for low voltage logic test switch t plh , t phl open t pzl , t plz v cc x 2 at v cc = 1.5v 0.1v t pzh , t phz gnd symbol v cc 1.5v 0.1v v mi v cc /2 v mo v cc /2 v x v ol + 0.1v v y v ol ? 0.1v
9 www.fairchildsemi.com 74vcx162244 physical dimensions inches (millimeters) unless otherwise noted 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide package number bga54a
www.fairchildsemi.com 10 74vcx162244 low voltage 16-bit buffer/line driver with 3.6v tolerant inputs and outputs and 26 ? series resistor in outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd48 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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